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Espressif Systems /ESP32-S3 /SPI2 /DMA_INT_SET

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Interpret as DMA_INT_SET

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMA_INFIFO_FULL_ERR_INT_SET)DMA_INFIFO_FULL_ERR_INT_SET 0 (DMA_OUTFIFO_EMPTY_ERR_INT_SET)DMA_OUTFIFO_EMPTY_ERR_INT_SET 0 (SLV_EX_QPI_INT_SET)SLV_EX_QPI_INT_SET 0 (SLV_EN_QPI_INT_SET)SLV_EN_QPI_INT_SET 0 (SLV_CMD7_INT_SET)SLV_CMD7_INT_SET 0 (SLV_CMD8_INT_SET)SLV_CMD8_INT_SET 0 (SLV_CMD9_INT_SET)SLV_CMD9_INT_SET 0 (SLV_CMDA_INT_SET)SLV_CMDA_INT_SET 0 (SLV_RD_DMA_DONE_INT_SET)SLV_RD_DMA_DONE_INT_SET 0 (SLV_WR_DMA_DONE_INT_SET)SLV_WR_DMA_DONE_INT_SET 0 (SLV_RD_BUF_DONE_INT_SET)SLV_RD_BUF_DONE_INT_SET 0 (SLV_WR_BUF_DONE_INT_SET)SLV_WR_BUF_DONE_INT_SET 0 (TRANS_DONE_INT_SET)TRANS_DONE_INT_SET 0 (DMA_SEG_TRANS_DONE_INT_SET)DMA_SEG_TRANS_DONE_INT_SET 0 (SEG_MAGIC_ERR_INT_SET)SEG_MAGIC_ERR_INT_SET 0 (SLV_BUF_ADDR_ERR_INT_SET)SLV_BUF_ADDR_ERR_INT_SET 0 (SLV_CMD_ERR_INT_SET)SLV_CMD_ERR_INT_SET 0 (MST_RX_AFIFO_WFULL_ERR_INT_SET)MST_RX_AFIFO_WFULL_ERR_INT_SET 0 (MST_TX_AFIFO_REMPTY_ERR_INT_SET)MST_TX_AFIFO_REMPTY_ERR_INT_SET 0 (APP2_INT_SET)APP2_INT_SET 0 (APP1_INT_SET)APP1_INT_SET

Description

SPI interrupt software set register

Fields

DMA_INFIFO_FULL_ERR_INT_SET

The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
DMA_OUTFIFO_EMPTY_ERR_INT_SET

The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
SLV_EX_QPI_INT_SET

The software set bit for SPI slave Ex_QPI interrupt.
SLV_EN_QPI_INT_SET

The software set bit for SPI slave En_QPI interrupt.
SLV_CMD7_INT_SET

The software set bit for SPI slave CMD7 interrupt.
SLV_CMD8_INT_SET

The software set bit for SPI slave CMD8 interrupt.
SLV_CMD9_INT_SET

The software set bit for SPI slave CMD9 interrupt.
SLV_CMDA_INT_SET

The software set bit for SPI slave CMDA interrupt.
SLV_RD_DMA_DONE_INT_SET

The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
SLV_WR_DMA_DONE_INT_SET

The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
SLV_RD_BUF_DONE_INT_SET

The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
SLV_WR_BUF_DONE_INT_SET

The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
TRANS_DONE_INT_SET

The software set bit for SPI_TRANS_DONE_INT interrupt.
DMA_SEG_TRANS_DONE_INT_SET

The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
SEG_MAGIC_ERR_INT_SET

The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.
SLV_BUF_ADDR_ERR_INT_SET

The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
SLV_CMD_ERR_INT_SET

The software set bit for SPI_SLV_CMD_ERR_INT interrupt.
MST_RX_AFIFO_WFULL_ERR_INT_SET

The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
MST_TX_AFIFO_REMPTY_ERR_INT_SET

The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
APP2_INT_SET

The software set bit for SPI_APP2_INT interrupt.
APP1_INT_SET

The software set bit for SPI_APP1_INT interrupt.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data